12. juni 2017
Webinar: Tuesday June 20, 2017, 10:00 – 12:00 hr – Register
The design effort for more complex FPGAs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. One way to address increased design complexity is to supplement traditional functional verification methods with assertion-based verification (ABV).
In this session you will learn:
- How to write SystemVerilog Assertions
- How to write PSL
- How to use OVL
- How to analyze all of them