28. august 2017
Advanced VHDL Verification – Made simple
Course 3-5 October, 2017, Business Centre Winghouse, Copenhagen.
Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, – and a good architecture is the answer. This applies for both Design and Verification.
On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is an intensive 3-day course on how to reduce development time and at the same time improve the quality.