Webinar: DDR memory system design verification and debug
In this webinar, we will be talking about the best practices of doing the DDR memory system design verification and debugging with an oscilloscope. Design and verification engineers will be learning the importance of ensuring a stable operation and of reducing the risk of failure after any change over the product’s lifetime. Both require a solid characterization of the memory interface.
We will be discussing test and tool requirements such as bandwidth, trigger and probing, which help with identifying jitter, timing and noise issues. With the help of the R&S®RTP high-performance oscilloscope, we will showcase practical measurement examples.
Speaker:
Hermann Ruckerbauer, CEO EyeKnowHow
Johannes Ganzert, Application Engineer Oscilloscopes, Rohde & Schwarz
Date:
Tuesday, September 15, 2020 – you can choose between 3 presentation times.
We look forward to seeing you there.
