Together with Inventas and Siemens, we invite FPGA developers, verification engineers, and digital designers to a free technical workshop featuring hands-on training, practical presentations, and discussions on modern verification methodologies.
From RTL Quality to Agentic AI: Practical FPGA Verification for Modern Development Teams.
This time, the program focuses on improving design quality earlier in the development cycle, advanced verification techniques using UVVM and UVM, processor design in VHDL, and how AI-powered verification tools are beginning to change everyday engineering workflows.
The day concludes with an afterwork and mingle session where you can exchange experiences and connect with fellow FPGA professionals. Register here.
