Free online UVM Framework and Questa Verification IP Session
UVM and VIP – Evolve your FPGA Verification Methodology
Attention FPGA Designers:
- Did your last FPGA design strech beyond the project schedule?
- Did your last FPGA have post production identified defects?
- Did your last FPGA require more than 3 iterations of lab debug?
Monday November 14, 14:00 – 15:00 CEST – Register
What you will learn:
Learn how to rapidly create a UVM Framework environment and how to incorporate the UVM Framework environment created by the Questa Verification IP Configurator.