Microsemi Corporation announces the availability of miTimePLL™, a new family of network synchronization phase-locked loops (PLLs) for Synchronous Ethernet (SyncE), IEEE 1588 and optical transport network (OTN). The new products have one third the jitter and half the footprint of current devices, which, in combination with the company’s new miTimePLL technology, is specifically designed to address the demands of phase alignment performance required by networks such as wireless infrastructure.
The standards for wireless infrastructure networks using 4G, LTE-A and future 5G are demanding more stringent performance. For example 3GPP calls for alignment better than 65 nanoseconds (ns) between base stations when using advanced technologies such as multiple input, multiple output (MIMO). The miTimePLL devices provide advanced network synchronization capabilities for phase alignment specifically for the wireless infrastructure.
Microsemi’s ZL307xx and ZL306xx family of network synchronization PLLs offers an impressive 180 femtoseconds (fs) typical jitter, ensuring a single chip, small footprint, low cost synchronization solution for 10GbE to 100GbE applications. These devices come with new features vital for network applications requiring phase alignment, including any-to-any frequency, better than 2 ns input/output (I/O) alignment, embedded 1 pulse per second (ePPS), time of day (ToD) registers, reference/synchronization inputs, and full monitoring and hitless reference switching between GPS/SyncE/1588. Microsemi’s ePPS is already providing a simple solution for chassis systems with limited backplane pins by combining phase into a high speed clock, thereby using a single pin, where before two were required.
For more information, visit http://www.microsemi.com/products/timing-and-synchronization/synchronous-ethernet-synce